Texas Instruments /MSP432P4011 /CS /CSCTL1

Selects the MCLK source

0 (SELM_0): when LFXT available, otherwise REFOCLK

1 (SELM_1): undefined

2 (SELM_2): undefined

3 (SELM_3): undefined

4 (SELM_4): undefined

5 (SELM_5): when HFXT available, otherwise DCOCLK

6 (SELM_6): when HFXT2 available, otherwise DCOCLK

7 (SELM_7): for future use. Defaults to DCOCLK. Not recommended for use

to ensure future compatibilities.

Selects the SMCLK and HSMCLK source

0 (SELS_0): when LFXT available, otherwise REFOCLK

1 (SELS_1): undefined

2 (SELS_2): undefined

3 (SELS_3): undefined

4 (SELS_4): undefined

5 (SELS_5): when HFXT available, otherwise DCOCLK

6 (SELS_6): when HFXT2 available, otherwise DCOCLK

7 (SELS_7): for furture use. Defaults to DCOCLK. Do not use to ensure future compatibilities.

Selects the ACLK source

0 (SELA_0): when LFXT available, otherwise REFOCLK

1 (SELA_1): undefined

2 (SELA_2): undefined

3 (SELA_3): for future use. Defaults to REFOCLK. Not recommended

for use to ensure future compatibilities.

4 (SELA_4): for future use. Defaults to REFOCLK. Not recommended

for use to ensure future compatibilities.

5 (SELA_5): for future use. Defaults to REFOCLK. Not recommended

for use to ensure future compatibilities.

6 (SELA_6): for future use. Defaults to REFOCLK. Not recommended

for use to ensure future compatibilities.

7 (SELA_7): for future use. Defaults to REFOCLK. Not recommended

for use to ensure future compatibilities.

Selects the BCLK source

0 (SELB_0): LFXTCLK

1 (SELB_1): REFOCLK

MCLK source divider

0 (DIVM_0): f(MCLK)/1

1 (DIVM_1): f(MCLK)/2

2 (DIVM_2): f(MCLK)/4

3 (DIVM_3): f(MCLK)/8

4 (DIVM_4): f(MCLK)/16

5 (DIVM_5): f(MCLK)/32

6 (DIVM_6): f(MCLK)/64

7 (DIVM_7): f(MCLK)/128

HSMCLK source divider

0 (DIVHS_0): f(HSMCLK)/1

1 (DIVHS_1): f(HSMCLK)/2

2 (DIVHS_2): f(HSMCLK)/4

3 (DIVHS_3): f(HSMCLK)/8

4 (DIVHS_4): f(HSMCLK)/16

5 (DIVHS_5): f(HSMCLK)/32

6 (DIVHS_6): f(HSMCLK)/64

7 (DIVHS_7): f(HSMCLK)/128

ACLK source divider

0 (DIVA_0): f(ACLK)/1

1 (DIVA_1): f(ACLK)/2

2 (DIVA_2): f(ACLK)/4

3 (DIVA_3): f(ACLK)/8

4 (DIVA_4): f(ACLK)/16

5 (DIVA_5): f(ACLK)/32

6 (DIVA_6): f(ACLK)/64

7 (DIVA_7): f(ACLK)/128

SMCLK source divider

0 (DIVS_0): f(SMCLK)/1

1 (DIVS_1): f(SMCLK)/2

2 (DIVS_2): f(SMCLK)/4

3 (DIVS_3): f(SMCLK)/8

4 (DIVS_4): f(SMCLK)/16

5 (DIVS_5): f(SMCLK)/32

6 (DIVS_6): f(SMCLK)/64

7 (DIVS_7): f(SMCLK)/128